This invention relates to methods and apparatuses for packaging microelectronic devices with reduced flash.
Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic device mounted to a substrate and encased in a plastic protective covering. The device includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The device also typically includes bond pads electrically coupled to the functional features. The bond pads are coupled to pins or other types of terminals that extend outside the protective covering for connecting the microelectronic device to busses, circuits and/or other microelectronic assemblies.
In one conventional arrangement, shown in FIG. 1, a device 40 is mounted to a substrate 20, such as a printed circuit board (xe2x80x9cPCBxe2x80x9d). The substrate 20 and the device 40 are placed in a mold 50 for encapsulation. The mold 50 can include an upper portion 51 removably attached to a lower portion 52 to define a device cavity 57, a pellet cavity 54, and a runner cavity 56 extending between the device cavity 57 and the pellet cavity 54. The substrate 20 is clamped between the upper portion 51 and the lower portion 52 with the device 40 positioned in the device cavity 57. A pellet of mold compound 60 is placed in the pellet cavity 54 and a plunger 55 forces the pellet 60 into the device cavity 57 via the runner cavity 56 to encapsulate the device 40.
Referring now to FIGS. 1 and 2, the substrate 20 has a first edge 21, a second edge 22 opposite the first edge 21, and drilled indexing holes 23 along both edges 21 and 22. The indexing holes 23 along the second edge 22 receive undersized index pins 53 when the substrate 20 is placed in the mold 50. An alignment pin 70 engages the second edge 22 and forces the substrate 20 toward the right (as seen in FIG. 1) so that the first edge 21 of the substrate 20 approaches an edge 59 of the mold 50 as the upper portion 51 and the lower portion 52 of the mold 50 move toward each other.
In one aspect of this conventional arrangement, the first edge 21 and the second edge 22 of the substrate 20 are routed with a router tool or formed by other low-cost processes. Accordingly, a width 29 of the substrate 20 between the first and second edges 21 and 22 can have a tolerance of xc2x1100 microns. One drawback with this approach is that the dimensional tolerance of the width 29 can lead to damaging the substrate 20 and/or forming flash around the encapsulated device 40. For example, if the substrate 20 has a width 29 toward the upper end of the tolerance range, it can buckle and/or break when the alignment pin 70 forces the substrate 20 against the mold edge 59. Conversely, if the substrate 20 has a width 29 toward the lower end of the tolerance range, a gap G can remain between the first edge 21 of the substrate and the mold edge 59, even after the alignment pin 70 has moved the substrate 20 toward the right. The gap G can fill with mold compound, creating a flange of flash extending outwardly from the first edge 21 of the substrate 20. The flash can interfere with subsequent processing steps, for example by catching on processing machines, or by separating from the substrate 20 and contaminating the machines.
The present invention is directed toward methods and apparatuses for encapsulating microelectronic devices. A method in accordance with one aspect of the invention includes providing a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The method can further include engaging the microelectronic device with the support member, positioning the first edge of the support member proximate to a wall of a mold, moving an aligning member relative to the wall of the mold and biasing the first edge of the support member against the wall of the mold by engaging the aligning member with the portion of the engaging surface spaced apart from the first and second edges. The method can further include at least partially encapsulating the microelectronic device by disposing an encapsulating material in the mold adjacent to the microelectronic device.
In a further aspect of the invention, the method can include forming the engaging surface to be spaced apart from the first surface of the support member by a selected distance having a tolerance of xc2x150 microns or less. Biasing the first edge of the support member against the wall of the cavity can include moving the aligning member in a direction either transverse to or aligned with a surface of the support member engaged with the microelectronic device.
The invention is also directed to a support member and method for forming a support member to support a microelectronic device. The support member can include a first edge configured to engage an interior wall of the mold, a second edge opposite the first edge, an electrically conductive material between the first and second edges for coupling to the microelectronic device, and an engaging surface. In one embodiment, the engaging surface is spaced apart from the first edge by a selected distance having a tolerance of xc2x150 microns or less and is configured to engage an alignment member of the mold when the support member and the microelectronic device are placed in the mold with the first edge of the support member engaged with the interior wall of the mold.